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EDGE818 Octal 18V Pin Electronics Driver/window Comparator
TEST AND MEASUREMENT PRODUCTS Description
The EDGE818 is an octal pin electronics driver and window comparator fabricated in a wide voltage CMOS process. It is designed specifically for Test During Burn In (TDBI) applications, where cost, functional density, and power are all at a premium. The EDGE818 incorporates eight channels of programmable drivers and window comparators into one 14 mm X 20 mm 100 pin MQFP package. Each channel has per pin driver levels, data, and high impedance control. In addition, each comparator has per pin high and low threshold levels. The EDGE818 uses "Flex In" and "Flex Out" digital inputs, and can therefore mate directly with any digital technology providing a minimum 2V swing. The digital outputs can mate directly with any digital technology. The 18V driver output and receiver input range allow the EDGE818 to interface directly with TTL, ECL, CMOS (3V, 5V, and 7V), LVCMOS, and custom level circuitry, as well as the high voltage (Super Voltage) level required for many special test modes for Flash Devices.
Features
* * * * * * * 18V I/O Range 50 MHz Operation Per Pin Flexibility Programmable Input Thresholds Flex In Digital Inputs Flex Out Digital Outputs Small footprint (100 pin MQFP)
Applications
* Burn In ATE * Low Cost ATE * Instrumentation
Functional Block Diagram
VH VL
DATA EN*
8 8
8
DOUT
QA COMP HIGH COMP LOW QB
8
- +
8
CVA
8
VINP
8
+ -
8 CVB
Revision 5 / August 18, 2004
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EDGE818
TEST AND MEASUREMENT PRODUCTS PIN Description
Pin Name DATA (0:7) Pin Number 100, 4, 8, 12, 19, 23, 27, 31 Description Digital inputs which determine the high/low state of the driver, when it is enabled. Digital inputs wihch enable/disable the driver. Comparator digital outputs.
EN* (0:7) QA (0:7) QB (0:7) DOUT (0:7)
3, 7, 11, 15, 16, 20, 24, 28 1, 5, 9, 13, 18, 22, 26, 30 2, 6, 10, 14, 17, 21, 25, 29 79, 75, 71, 67, 64, 60, 56, 52
Driver Outputs.
VINP (0:7) VH (0:7)
81, 77, 73, 69, 62, 58, 54, 50 80, 76, 72, 68, 63, 59, 55, 51
Comparator Inputs. Unbuffered analog inputs that set the driver "high" voltage level. Unbuffered analog inputs that set the driver "low" voltage level. Analog inputs that set the threshold for the A comparators.
VL (0:7)
78, 74, 70, 66, 65, 61, 57, 53
CVA (0:7)
97, 95, 89, 87, 44, 42, 36, 34
CVB (0:7) VBB
96, 94, 88, 86, 45, 43, 37, 35 46, 85
Analog inputs that set the threshold for the B comparators. Analog input voltage that sets the threshold for the digital inputs. Unbuffered analog input that sets the high level of the comparator outputs. Unbuffered analog input that sets the low level of the comparator outputs. Positive power supply.
COMP HIGH
33, 98
COMP LOW
32, 99
VCC
40, 41, 47, 49, 82, 84, 90, 91
VEE
38, 39, 48, 83, 92, 93
Negative power supply.
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EDGE818
TEST AND MEASUREMENT PRODUCTS PIN Description (continued)
COMP HIGH COMP LOW
DATA0
81 QA0 QB0 EN*0 DATA1 QA1 QB1 EN*1 DATA2 QA2 QB2 EN*2 DATA3 QA3 QB3 EN*3 EN*4 QB4 QA4 DATA4 EN*5 QB5 QA5 DATA5 EN*6 QB6 QA6 DATA6 EN*7 QB7 QA7 31 51 1 VH0 DOUT0 VL0 VINP1 VH1 DOUT1 VL1 VINP2 VH2 DOUT2 VL2 VINP3 VH3 DOUT3 VL3 VL4 DOUT4 VH4 VINP4 VL5 DOUT5 VH5 VINP5 VL6 DOUT6 VH6 VINP6 VL7 DOUT7 VH7
100 Lead - 14 x 20 MQFP
DATA7
VEE
VEE
VBB
CVA7
CVA6
CVA5
CVB7
CVB6
CVB5
CVA4
VCC
VCC
CVB4
VEE
COMP LOW
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COMP HIGH
3
VINP7
VCC
VCC
VINP0
CVB0
CVB1
CVB2
CVB3
CVA0
CVA1
CVA2
CVA3
VCC
VCC
VCC
VCC
VEE
VEE
VBB
VEE
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EDGE818
TEST AND MEASUREMENT PRODUCTS Circuit Description
VH
Driver Description The EDGE818 supports programmable high and low levels and tristate per channel. There are no shared lines between any drivers. The EN* and DATA signals are wide voltage high impedance analog inputs capable of receiving digital signals over a wide common mode range. VBB is the high impedance analog input which sets the threshold for EN* and DATA.
VL
DUT
EN*, DATA > VBB < VBB
Status "1" "0"
Figure 1. Simplified Model of the Unbuffered Output Stage
With EN* high, the driver goes into a high impedance state. With EN* low, DATA high forces the driver into a high state, and DATA low forces the driver into a low state. EN* 1 0 0 DATA X 1 0 DOUT HiZ VH VL
Driver Output Protection In a functional testing environment, where a resistor is added in series with the driver output to create a 50 driver, the EDGE818 can withstand a short to any legal voltage for an indefinite amount of time. In a low impedance application, with no additional output resistance, the system should be designed to check for a short circuit prior to connecting the driver, and tristate the driver if a short is detected.
Drive High and Low VH and VL define the logical "1" and "0" levels of the driver, and can be adjusted anywhere over the range determined by VCC and VEE. There are no restrictions between VH and VL, other than they must remain within the power supply levels. VEE VEE VH VCC VL VCC
Receiver Description The EDGE818 supports a window comparator with independent threshold levels per channel. There are no shared comparator lines between channels. CVA and CVB are high impedance analog voltage inputs which define the threshold voltages for comparators A and B. If VINP is more positive than CVA or CVB, QA and QB will be high. Otherwise, QA and QB will be low. VINP VINP > CVA VINP < CVA VINP VINP > CVB VINP < CVB QA COMP HIGH COMP LOW QB COMP HIGH COMP LOW
The VH and VL inputs are unbuffered in that they also provide the driver output current (see Figure 1), so the source of VH and VL must have ample current drive capability.
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EDGE818
TEST AND MEASUREMENT PRODUCTS Circuit Description (continued)
The comparator outputs are "Flex Out". They are technology independent and may be adjusted over a wide voltage common mode range. COMP HIGH and COMP LOW are analog inputs which set the digital high and low levels (respectively) of QA and QB. COMP HIGH and COMP LOW are unbuffered inputs that provide the necessary drive current, so the sources for these levels must have adequate current capability.
COMP HIGH
QAX, QBX
COMP LOW
Figure 2. Simplified Model of the Unbuffered Comparator Output Stage
Typically, COMP HIGH and COMP LOW will be connected to the digital power supplies of the chip receiving QA and QB. Receiver Headroom There is ~3V of headroom required between the comparator thresholds and both power supply levels. VEE + 3.0 CVA, CVB VCC - 3.0
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EDGE818
TEST AND MEASUREMENT PRODUCTS Application Information
Power Supply Decoupling VCC and VEE should be decoupled to GND with a .1 F chip capacitor in parallel with a .001 F chip capacitor. A VCC and VEE plane, or at least a solid power bus, is recommended for optimal performance. VH and VL Decoupling As the VH and VL inputs are unbuffered and supply the driver output current, which can be quite large during edge transitions, decoupling capacitors for these inputs are recommended in proportion to the amount of output current requirements. For applications where VH and VL are shared over multiple channels, a solid power plane to distribute these levels is preferred. VBB The two VBB pins are connected together on-chip. Therefore, only one VBB needs to be connected to for proper 818 operation. The two pins may be used to daisy chain a VBB signal across a PC Board without having to route the actual signal underneath the 818. Power Supplies The EDGE818 has several power supply requirements to protect the part in power supply fault situations, as well as during power up and power down sequences. The following power supply requirements must be satisfied at all times: VEE All I/O pins VCC at all times. The power sequence below can be used as a guideline when operating the EDGE818: Power-on Sequencing 1. VCC (substrate) 2. VEE 3. I/O Pins Power-off Sequencing 1. I/O Pins 2. VEE 3. VCC
The three diode configuration shown in Figure 3 should be used on a once-per-board basis.
VCC
External Logic Supply
VDD 1N5820 or Equivalent
External System Ground
VEE
Figure 3. Power Supply Protection Scheme
gure 5. Warning: It is extremely important that the voltage on any device pin does not exceed the range of VEE -0.5V to VCC +0.5V at any time, either during power up, normal operation, or during power down. Failure to adhere to this requirement could result in latchup of the device, which could be destructive if the system power supplies are capable of supplying large amounts of current. Even if the device is not immediately destroyed, the cumulative damage caused by the stress of repeated latchup may affect device reliability.
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EDGE818
TEST AND MEASUREMENT PRODUCTS Application Information (continued)
Power Dissipation/Thermal Considerations The EDGE818 is specified to operate with a die junction temperature, Tj, of up to 125C. The theoretical junction temperature is calculated as follows: Tj = Tc + jc x Ptotal Where Tj = The Theoretical Junction Temperature of the EDGE818 [C] = The Case Temperature of the Tc EDGE818[C] jc = The Thermal Impedance of the EDGE818 (junction to top center of case)[C] Ptotal = The Total Power Dissipation of the EDGE818 [W] relatively large power savings when using the device is to minimize the power supply levels that are used for a particular application. (Note that varying power supply levels may have an effect on device propagation delays and driver output impedance.) For illustrative purposes, this approach to power savings is evaluated on the following application: Example: The EDGE818 is used to generate 3.3V output swings on all 8-channels simultaneously under the following conditions: * * * * VL = 0V VH = 3.3V f = 25 MHz Zload = 1k||80pF
In order to maximize the reliability and operating lifetime of the EDGE818, the junction temperature of the device should be minimized. It can be seen from the equation above that the junction temperature of the EDGE818 is both a function of its case temperature and the total power dissipation of the device. Therefore, one can minimize the junction temperature of the EDGE818 by minimizing the case temperature and the overall power dissipation of the device. The case temperature of the EDGE818 can be controlled through the use of some source of external cooling to regulate the case temperature (i.e. forced air). A heat sink can also be attached to the EDGE818 in order to maximize the efficiency and increase the overall heat capacity of the external cooling used in an application. A heat sink can be attached to the top of the device, and/ or additional cooling can be attained through the bottom of the device (i.e. into a copper plane on the PCB or a heat sink attached to the device through a hole in the PCB). This will significantly decrease the effective thermal resistance between the case of the EDGE818 and the cooling mechanism being used. The total power dissipation of the EDGE818 can also be minimized, but is ultimately dependent upon the requirements of the application. One way to attain a
Under the conditions above, the power dissipation of the EDGE818 is as depicted in Table 1.
VCC[V] 12 7.5
VEE[V] -3.3 -4.6
VCC-VEE[V] 15.3 12.1
Pdiss[W] 3.4 2.2
Tj[C] 77 59
Table 1. Comparison of EDGE818 Power Dissipation and Junction Temperature at f = 25 MHz, Ta = 25 C, Airflow = 300 LFPM
Note that by reducing the power supply levels in the application depicted above, a power savings of 1.2W was realized (and Tj was reduced by 18C). The power dissipation (and hence Tj) of the EDGE818 is directly proportional to its operating frequency. This is illustrated in Figures 4 and 5.
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EDGE818
TEST AND MEASUREMENT PRODUCTS Application Information (continued)
Edge 818AHF Power Dissipation vs. Frequency
4.00
3.50
3.00
2.50 A/L B057 2.00 A/L B076 A/L 2131 1.50
1.00
0.50
0.00 0 5 10 15 Frequency [Mhz] 20 25 30
Figure 4. EDGE818 Power Dissipation vs. Operating Frequency (VCC = 12V, VEE = -3.3V, VH = 3.3V, VL = 0V, Zload = 1K\\80pF, Ta = 25C, Airflow = 300 LFPM, All 8 Driver Channels Toggled)
Edge 818 AHF Junction Temperature vs. Operating Frequency
90 80 70 60 50 40 30 20 10 0 0 5 10 15 Frequency [MHz] 20 25 30 A/L B057 A/L B076 A/L 2131
Figure 5. EDGE818 Junction Temperature vs. Operating Frequency (VCC = 12V, VEE = -3.3V, VH = 3.3V, VL = 0V, Zload = 1K||80pF, Ta = 25C, Airflow = 300 LFPM, All 8 Driver Channels Toggled)
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Junction Temperature, Tj [Deg. C]
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EDGE818
TEST AND MEASUREMENT PRODUCTS Application Information (continued)
Driving a Resistive Load In addition to the VCC and VEE power supply levels, the "driver high" (VH) and "driver low" (VL) levels used in an application also have an effect on the total power dissipation of the device illustrated using Figure 6.
External "Driver High" Buffer
Therefore, the per-channel power dissipation due to the EDGE818 driving and resistive load is: P = [IL(H) x Rds(H) x D + IL(L)] x [Rds(L) x (1-D)] where P
VH
Rds(H)
Simplified EDGE818 Output Stage
H
DOUT
IL
L RT Rds(L)
= The total power dissipated by the EDGE818 as a result of the resistive load, RL [W] IL(H) = The amount of current required by RL during a logic "high" state [A] Rds(H) = The output impedance of the EDGE818 driver when driving a logic "high" state [] D = The normalized amount of time that logic "high" is driven (Duty Cycle) IL(L) = The amount of current required by RL during a logic "low" state [A] Rds(L) = The output impedance of the EDGE818 driver when driving a logic "low" state []
VT
VL
External "Driver Low" Buffer
Figure 6. Simplified Functional Schematic of EDGE818 Output Stage and External Buffers
The CMOS switches of the EDGE818's output stage have on-resistance values (depicted by Rds(H) and Rds(L) in Figure 6) that vary as a function of VH and VL voltage levels. The amount of current required by the load impedance, RT, is also a function of the VH and VL voltage levels as follows: Switch in Figure 6 is in position "H": IL(H) = VH - VT Rds(H) + RT
Switch in Figure 6 is in position "L": IL(L) = VL - VT Rds(L) + RT
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EDGE818
TEST AND MEASUREMENT PRODUCTS Package Information
100-Pin MQFP 14 mm x 20 mm
4 D D2 Z D -D- 3
PIN Descriptions
4X
0.25
C
A-B
D
3 e
-A-
-B-
3
E2 -E- 4
Z
E
SEE DETAIL "A"
TOP VIEW
2 4X
5
7 0.20 C A-B 5 D1 D 7
5
7
E1
O
O
BOTTOM VIEW
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C
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EDGE818
TEST AND MEASUREMENT PRODUCTS Package Information (continued)
0.40 MIN. 0 MIN.
e/2
A2 - 0.10 S 0.13 / 0.30 R. TYP. 0.13 R. MIN. C
-A, B, D-
3
GAGE PLANE
C
DETAIL "A"
A1 BASE PLANE SEATING PLANE 1.60 REF.
L
0.25
0-7
DETAIL "B"
12 - 16 1.28 REF.
SEE DETAIL "B" A B -H- 2 0.076 -C- 12 0.13 / 0.23
8
ccc
M
C A-B S D S
WITH LEAD FINISH
0.13 / 0.17
12 - 16
SECTION C-C
B
1 BASE METAL
Variations (all dimensions in millimeters) Notes: 1. All dimensions and tolerances conform to ANSI Y14.5-1982. 2. Datum plane -H- located at mold parting line and coincident with lead, where lead exits plastic body at bottom of parting line. 3. Datums A-B and -D- to be determined where centerline between leads exits plastic body at datum plane -H-. 4. To be determined at seating plane -C-. 5. Dimensions D1 and E1 do not include mold protrusion. Allowable mold protrusion is 0.254 mm per side. Dimensions D1 and E1 do include mold mismatch and are determined at datum plane -H-. 6. "N" is the total # of terminals. 7. Package top dimensions are smaller than bottom dimensions and top of package will not overhang bottom of package. 8. Dimension B does not include dambar protrusion. Allowable dambar protrusion shall be 0.08 mm total in excess of the dimension at maximum material condition. Dambar cannot be located on the lowerradius or the foot. 9. All dimensions are in millimeters. 10. Maximum allowable die thickness to be assembled in this package family is 0.635 millimeters. 11. This drawing conforms to JEDEC registered outlines MS-108 and MS-022. 12. These dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm from the lead tip. 2004 Semtech Corp. / Rev. 5, 8/18/04
Symbol A A1 A2 D D1 D2 ZD E E1 E2 ZE L N e B B1 ccc ND NE 0.22 0.22 0.30 0.13 30 20 Side Pin Count Side Pin Count 0.73 0.25 2.57 Min Nom 3.04 0.33 2.71 23.20 BSC 20.00 BSC 18.85 REF 0.58 REF 17.20 14.00 BSC 12.35 REF 0.83 REF 0.88 100 0.65 BSC 0.38 0.33 8 1.03 6 Pin Count Lead Pitch Pad Dimension Pad Dimension 4 5 Body Dimension 2.87 4 5 Body Dimension Max 3.40 Note Comments Height above PCB Gap above PCB Body Thickness
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EDGE818
TEST AND MEASUREMENT PRODUCTS Recommended Operating Conditions
Parameter Total Analog Supply Ambient Operating Temperature Junction Temperature Thermal Resistance of Package (Junction to Still Air) Thermal Resistance of Package (Junction to Case) Symbol VCC - VEE TA TJ JA JC 32.2 12.4 Min 12.0 Typ Max 18.0 +70 +125 Units V
oC oC oC/W oC/W
Absolute Maximum Ratings
Parameter Total Power Supply Digital Input Voltages Analog Input Voltages Analog Output Voltages Symbol VCC - VEE DATA, EN* VH, VL, CVA, CVB, VINP, VBB DOUT, COMP HIGH, COMP LOW Min -0.5 VEE - .5 VEE - .5 VEE - .5 Max 19.0 VCC + .5 VCC + .5 VCC + .5 Units V V V V
Ambient Operating Temperature Storage Temperature Junction Temperature Soldering Temperature (5 seconds, .25" from the pin)
TA TS TJ TSOL
-50 -65
+125 +150 +150 +260
oC oC oC oC
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these, or any other conditions beyond those listed, is not implied. Exposure to absolute maximum conditions for extended periods may affect device reliability.
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EDGE818
TEST AND MEASUREMENT PRODUCTS DC Characteristics
Parameter Driver High Voltage Low Voltage Output Swing HiZ Leakage Current Output Impedance DC Output Current (Note 1) AC Output Current (Note 2) Receiver Input Voltage Range Threshold Voltage Range Offset Voltage (Note 3) Input Bias Current Output Voltage Range QA, QB Output Impedance DC Output Current Capability Digital Inputs Input High Voltage Input Low Voltage Input Current Power Supplies Positive Supply Current (Note 4) Negative Supply Current (Note 4) ICC IEE 36 36 57 57 78 78 mA mA EN*, DATA - VBB VBB - EN*, DATA Iin 1.0 1.0 - 100 V V nA VINP CVA, CVB Vos Ibias COMP HIGH COMP LOW Rout VEE VEE + 3.0 - 200 - 10 - 2.0 - 2.0 30 -50 40 VCC VCC - 3.0 +100 +10.0 +5.0 +5.0 50 50 V V mV nA V V mA VH VL VH - VL Ileak Rout Iout DC Iout AC VEE VEE - 18 - 2.0 9.0 - 125 - 400 VCC VCC 18 +2.0 15 +125 +400 V V V nA mA mA Symbol Min Typ Max Units
0 12
0
0
+100
Test conditions (unless otherwise specified): "Recommended Operating Conditions". Note Note Note Note 1: 2: 3: 4: DC output current is specified per individual driver. Surge current capability for durations of < 2 seconds. Offset voltage is tested at CVA, CVB = 1.5V. Power supply current tested with VCC = +15V, VEE = -3V.
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EDGE818
TEST AND MEASUREMENT PRODUCTS AC Characteristics
Parameter Driver DATA to DOUT EN* to DOUT (Active to HiZ) (Note 1) EN* to DOUT (HiZ to Active) Rise/Fall Times (Note 2) 1V Swing (20% - 80%) 3V Swing (10% - 90%) 5V Swing (10% - 90%) 10V Swing (10% - 90%) 15V Swing (10% - 90%) Maximum Operating Frequency (Note 3) Minimum Pulse Width DOUT Capacitance Receiver Comparator Propagation Delay (Note 4) Tpd+ (Positive Edge) VINP - CVA(B) = 0.2V VINP - CVA(B) = 0.3V VINP - CVA(B) = 0.4V VINP - CVA(B) = 1.5V VINP - CVA(B) 1.5V Tpd- (Negative Edge) VINP - CVA(B) = 0.2V VINP - CVA(B) = 0.3V VINP - CVA(B) = 0.4V VINP - CVA(B) = 1.5V VINP - CVA(B) 1.5V Maximum Operating Frequency (Note 3) Minimum Pulse Width VINP Capacitance CV I N P Fmax Tpd 23.3 19.0 17.0 9.7 8.0 28.5 22.5 22.0 14.5 10.0 50 10 6 15 49.7 41.0 36.0 20.7 20.7 58.5 47.5 41.6 23.5 23.5 ns ns ns ns ns ns ns ns ns ns MHz ns pF CD O U T Tpd Tpd Tpd Tr/Tf Tr/Tf Tr/Tf Tr/Tf Tr/Tf Fmax 50 8 19 11 9.5 10 11 14.5 20 16 1.5 1.9 2.0 2.5 3.2 19.5 30 21 ns ns ns ns ns ns ns ns MHz ns pF Symbol Min Typ Max Units
Test conditions (unless otherwise specified): "Recommended Operating Conditions". Note 1: Note 2: Note 3: Note 4: Load = 10 mA and measured when a 1V change at the output is detected. (VH = 3V, VL = 0V, VFLOAT = 1.5V, tested at 1V and 2V.) Into 18 cm of 50 transmission line terminate with 1 K, with proper series termination resistor. Guaranteed by characterization. This parameter is not tested in production. This parameter is production tested at 40 MHz. Tested under no-load conditions.
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EDGE818
TEST AND MEASUREMENT PRODUCTS Ordering Information
Model Number E818AHF
Package 100 Lead MQFP 14 mm x 20 mm Body Size w/Internal Heat Spreader
EVM818AHF
EDGE818 Evaluation Board
Contact Information
Semtech Corporation Test and Measurement Division 10021 Willow Creek Rd., San Diego, CA 92131 Phone: (858)695-1808 FAX (858)695-2633
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